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NBSG53A 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS*
The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by two (DIV/2) clock generator. This is a part of the GigaCommTM family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package. The NBSG53A is a device with data, clock, OLS, reset, and select inputs. Differential inputs incorporate internal 50 W termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS/LVTTL input levels. Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device.
http://onsemi.com MARKING DIAGRAM**
SG 53A LYW FCBGA-16 BA SUFFIX CASE 489
QFN-16 MN SUFFIX CASE 485G
SG53A ALYW
* Maximum Input Clock Frequency (DFF) > 8 GHz Typical * * * * * * * * *
(See Figures 4, 6, 8, 10, and 11) Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical (See Figures 5, 7, 9, 10, and 11) 210 ps Typical Propagation Delay (OLS = FLOAT) 45 ps Typical Rise and Fall Times (OLS = FLOAT) DIV/2 Mode (Active with Select Low) DFF Mode (Active with Select High) Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak-to-Peak Output) 50 W Internal Input Termination Resistors on all Differential Inputs
Board NBSG53ABAEVB
A = Assembly Location L = Wafer Lot Y = Year W = Work Week
**For further details, refer to Application Note AND8002/D
Description NBSG53ABA Evaluation Board
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet.
*Output Level Select
(c) Semiconductor Components Industries, LLC, 2004
1
March, 2004 - Rev. 5
Publication Order Number: NBSG53A/D
NBSG53A
1 A
VTD
2
D
3
D
4
VTD
VCC 16 VTCLK
R 15
SEL OLS 14 13 Exposed Pad (EP) 12 11 VEE Q Q VCC
1 2 NBSG53A 3 4
B
CLK
VTCLK
VCC
Q
CLK
Q
C
CLK
VTCLK
VEE
CLK VTCLK
10 9
D
VCC
R
SEL
OLS
5 VTD
6 D
7 D
8 VTD
Figure 1. BGA-16 Pinout (Top View) Table 1. Pin Description
Pin BGA C2 C1 QFN 1 2 Name VTCLK CLK I/O - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - RSECL Output RSECL Output - Input LVECL, LVCMOS, LVTTL Input LVECL, LVCMOS, LVTTL Input
Figure 2. QFN-16 Pinout (Top View)
Description Internal 50 W Termination Pin. See Table 4. Inverted Differential Input.
B1
3
CLK
Noninverted Differential Input.
B2 A1 A2
4 5 6
VTCLK VTD D
Internal 50 W Termination Pin. See Table 4. Internal 50 W termination pin. See Table 4. Inverted Differential Input.
A3
7
D
Noninverted Differential Input.
A4 D1,B3 B4 C4 C3 D4 D3
8 9,16 10 11 12 13 14
VTD VCC Q Q VEE OLS* SEL
Internal 50 W Termination Pin. See Table 4. Positive Supply Voltage Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC - 2 V. Noninverted Differential Output. Typically Terminated with 50 W Resistor to VTT = VCC - 2 V. Negative Supply Voltage Input Pin for the Output Level Select (OLS). See Table 2. Select Logic Input. Internal 75 kW to VEE.
D2
15
R
Reset D Flip-Flop. Internal 75 kW to VEE.
N/A
-
EP
Exposed Pad. (Note 1)
1. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit. 2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage, and if no signal is applied then the device will be susceptible to self-oscillation. 3. When an output level of 400 mV is desired and VCC - VEE > 3.0 V, 2KW resistor should be connected from OLS pin to VEE.
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NBSG53A
VCC
OLS VTD 50 W D D 50 W VTD 2 2 D Flip-Flop (DFF) R 2 2 VTCLK 50 W CLK CLK 50 W VTCLK R SEL 75 kW 75 kW 2 R D Q Flip-Flop (DIV/2) Q 2
1 0
2
Q Q
VEE
Figure 3. Simplified Logic Diagram Table 2. OUTPUT LEVEL SELECT (OLS)
OLS VCC VCC - 0.4 V VCC - 0.8 V VCC - 1.2 V VEE (Note 4) Float Q/Q VPP 800 mV 200 mV 600 mV 0 400 mV 600 mV OLS Sensitivity OLS - 75 mV OLS $ 150 mV OLS $ 100 mV OLS $ 75 mV OLS + 100 mV N/A
Table 3. TRUTH TABLE
R H L L L SEL x H H L D x L H x CLK x Z Z Z Q L L H Q Function Reset DFF DFF DIV/2
Z = LOW to HIGH Transition
4. When an output level of 400 mV is desired and VCC - VEE > 3.0 V, 2.0 kW resistor should be connected from OLS to VEE.
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS CML LVDS AC-COUPLED RSECL, PECL, NECL LVTTL, LVCMOS CONNECTIONS Connect VTCLK, VTD and VTCLK, VTD to VCC Connect VTCLK, VTD and VTCLK, VTD Together Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (VIHCMR) Standard ECL Termination Techniques An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal VTHR is 1.5 V for LVTTL and VCC/2 for LVCMOS Inputs. This Voltage must be within the VTHR Specification.
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NBSG53A
Table 5. ATTRIBUTES
Characteristics Positive Operating Voltage Range for VCC (VEE = 0 V) Negative Operating Voltage Range for VEE (VCC = 0 V) Internal Input Pulldown Resistor (R, SEL) ESD Protection Human Body Model Machine Model Charged Device Model 16-FCBGA 16-QFN Value 2.375 V to 3.465 V -2.375 V to -3.465 V 75 kW > 1.5 kV > 50 V > 4 kV Level 3 Level 1 UL 94 V-0 @ 0.125 in 28 to 34 482
Moisture Sensitivity (Note 5) Flammability Rating Oxygen Index Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 5. For additional information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol VCC VEE VI VINPP IIN IOUT TA Tstg qJA Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage |D - D| Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VCC - VEE w VCC - VEE < Static Surge Continuous Surge 16 FCBGA 16 QFN 2.8 V 2.8 V VI v VCC VI w VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 |VCC - VEE| 45 80 25 50 -40 to +70 -40 to +85 -65 to +150 0 LFPM 500 LFPM 0 LFPM 500 LFPM 2S2P (Note 6) 2S2P (Note 7) < 15 Seconds 16 FCBGA 16 FCBGA 16 QFN 16 QFN 16 FCBGA 16 QFN 108 86 41.6 35.2 5.0 4.0 225 Units V V V V V V mA mA mA mA C C C/W C/W C/W C/W C/W C/W C
Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 6)
qJC Tsol
Thermal Resistance (Junction-to-Case) Wave Solder
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 6. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power). 7. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG53A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 8)
-40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 9) Output LOW Voltage (Note 9) (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) Output Voltage Amplitude (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) VIH VIL VIH VIL VTHR VIHCMR Input HIGH Voltage (Single-Ended) (Notes 11 and 13) CLK, CLK, D, D Input LOW Voltage (Single-Ended) (Notes 12 and 13) CLK, CLK, D, D Input High Voltage (Single-Ended) R, SEL Input Low Voltage (Single-Ended) R, SEL Input Threshold Voltage (Single-Ended) (Note 13) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) Internal Input Termination Resistor Input HIGH Current (@VIH) R, SEL CLK, CLK, D, D Input LOW Current (@VIL) R, SEL CLK, CLK, D, D 715 125 525 0 325 VEE + 1275 VEE 805 215 615 5 415 VCC - 1000* VCC- 1400* VCC VIH- 150 VCC 890 VCC- 75 2.5 705 120 520 0 320 VEE + 1275 VEE 795 210 610 0 410 VCC - 1000* VCC- 1400* VCC VIH- 150 VCC 955 VCC- 75 2.5 700 120 515 0 320 VEE + 1275 VEE 790 210 605 5 410 VCC- 1000* VCC- 1400* VCC VIH- 150 VCC mV VEE VEE+ 1125 1.2 VEE VEE+ 1125 1.2 VEE VEE+ 1125 1.2 1015 VCC- 75 2.5 mV V mV mV mV 1290 1355 1415 Min 33 1460 555 1235 775 1455 1005 Typ 45 1510 705 1295 895 1505 1095 Max 57 1560 855 1355 1015 1555 1185 Min 33 1490 595 1270 810 1490 1040 25C Typ 45 1540 745 1330 930 1540 1130 Max 57 1590 895 1390 1050 1590 1220 70C(BGA)/85C(QFN)** Min 33 1515 625 1295 840 1510 1065 Typ 45 1565 775 1355 960 1560 1155 Max 57 1615 925 1415 1080 1610 1245 mV Unit mA mV mV
VOUTPP
RTIN IIH IIL
45
50 35 5 20 5
55 100 50 100 50
45
50 35 5 20 5
55 100 50 100 50
45
50 35 5 20 5
55 100 50 100 50
W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to -0.965 V. 9. All outputs loaded with 50 W to VCC - 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 11. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 12. VIL always w VEE. |VIL - VTHR| < 2600 mV. 13. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C.
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NBSG53A
Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 14)
-40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 15) Output LOW Voltage (Note 15) (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) Output Amplitude Voltage (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) VIH VIL VIH VIL VTHR VIHCMR Input HIGH Voltage (Single-Ended) (Notes 17 and 19) CLK, CLK, D, D Input LOW Voltage (Single-Ended) (Notes 18 and 19) CLK, CLK, D, D Input High Voltage (Single-Ended) R, SEL Input Low Voltage (Single-Ended) R, SEL Input Threshold Voltage (Single-Ended) (Note 19) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 16) Internal Input Termination Resistor Input HIGH Current (@VIH) R, SEL CLK, CLK, D, D Input LOW Current (@VIL) R, SEL CLK, CLK, D, D 750 130 550 0 345 VEE + 1275 VIH- 2600 2090 VEE VEE+ 1125 1.2 840 220 640 0 435 VCC - 1000* VCC- 1400* VCC VIH- 150 VCC 1690 VCC- 75 3.3 740 125 545 0 340 VEE + 1275 VIH- 2600 2155 VEE VEE+ 1125 1.2 830 215 635 0 430 VCC - 1000* VCC- 1400* VCC VIH- 150 VCC 1755 VCC- 75 3.3 735 125 540 0 335 VEE + 1275 VIH- 2600 2215 VEE VEE+ 1125 1.2 825 215 630 0 425 VCC - 1000* VCC- 1400* VCC VIH- 150 VCC mV 1815 VCC- 75 3.3 mV V mV mV mV Min 35 2260 1320 2030 1550 2260 1785 Typ 47 2310 1470 2090 1670 2310 1875 Max 59 2360 1620 2150 1790 2360 1965 Min 35 2290 1360 2065 1585 2290 1820 25C Typ 47 2340 1510 2125 1705 2340 1910 Max 59 2390 1660 2185 1825 2390 2000 70C(BGA)/85C(QFN)*** Min 35 2315 1390 2090 1615 2315 1850 Typ 47 2365 1540 2150 1735 2365 1940 Max 59 2415 1690 2210 1855 2415 2030 mV Unit mA mV mV
VOUTPP
RTIN IIH IIL
45
50 35 5 20 5
55 100 50 100 50
45
50 35 5 20 5
55 100 50 100 50
45
50 35 5 20 5
55 100 50 100 50
W mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.165 V. 15. All outputs loaded with 50 W to VCC - 2.0 V. 16. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 17. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 18. VIL always w VEE. |VIL - VTHR| < 2600 mV. 19. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C.
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NBSG53A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 20) -40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 21) Output LOW Voltage (Note 21) -3.465 V v VEE v -3.0 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS =FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) -3.0 V < VEE v -2.375 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS =FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) Output Voltage Amplitude -3.465 V v VEE v -3.0 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) **(OLS = VEE) -3.0 V < VEE v -2.375 V (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS =FLOAT) (OLS = VCC - 1.2 V) (OLS = VEE) Input HIGH Voltage (Single-Ended) (Notes 23 and 25) CLK, CLK, D, D Input LOW Voltage (Single-Ended) (Notes 24 and 25) CLK, CLK, D, D Input High Voltage (Single-Ended) R, SEL VIL VTHR Input Low Voltage (Single-Ended) R, SEL Input Threshold Voltage (Single-Ended) (Note 25) -1210 VEE VEE+ 1125 VCC -1610 VCC- 75 -1145 VEE VEE+ 1125 VCC -1545 VCC- 75 -1085 VEE VEE+ 1125 VCC mV -1485 VCC- 75 mV Min 35 -1040 Typ 47 -990 Max 59 -940 Min 35 -1010 25C Typ 47 -960 Max 59 -910 70C(BGA)/85C(QFN)*** Min 35 -985 Typ 47 -935 Max 59 -885 Unit mA mV mV -1980 -1270 -1750 -1040 -1515 -1945 -1265 -1725 -1045 -1495 -1830 -1210 -1630 -990 -1425 -1795 -1205 -1605 -995 -1405 -1680 -1150 -1510 -940 -1335 -1645 -1145 -1485 -945 -1315 -1940 -1235 -1715 -1010 -1480 -1905 -1230 -1690 -1010 -1460 -1790 -1175 -1595 -960 -1390 -1755 -1170 -1570 -960 -1370 -1640 -1115 -1475 -910 -1300 -1605 -1110 -1450 -910 -1280 -1910 -1210 -1685 -985 -1450 -1875 -1205 -1660 -990 -1435 -1760 -1150 -1565 -935 -1360 -1725 -1145 -1540 -940 -1345 -1610 -1090 -1445 -885 -1270 -1575 -1085 -1420 -890 -1255 mV 750 130 550 0 345 715 125 525 0 325 VEE + 1275 VIH- 2600 840 220 640 0 435 805 215 615 5 415 VCC - 1000* VCC- 1400* VCC VIH- 150 740 125 545 0 340 705 120 520 0 320 VEE + 1275 VIH- 2600 830 215 635 0 430 795 210 610 0 410 VCC - 1000* VCC- 1400* VCC VIH- 150 735 125 540 0 335 700 120 515 0 320 VEE + 1275 VIH- 2600 825 215 630 0 425 790 210 605 5 410 VCC - 1000* VCC- 1400* VCC VIH- 150 mV mV mV
VOUTPP
VIH VIL VIH
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Input and output parameters vary 1:1 with VCC. 21. All outputs loaded with 50 W to VCC - 2.0 V. 22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 23. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 24. VIL always w VEE. |VIL - VTHR| < 2600 mV. 25. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C.
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NBSG53A
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
VCC = 0 V; VEE = -3.465 V to -2.375 V (Note 20) (continued) -40C Symbol VIHCMR Characteristic Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 22) Internal Input Termination Resistor Input HIGH Current (@VIH) R, SEL CLK, CLK, D, D IIL Input LOW Current (@VIL) R, SEL CLK, CLK, D, D IOLS OLS Input Current (See Figure 12) (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) (OLS = VCC - 1.2 V) -3.465 V v VEE v -3.0 V *(OLS = VEE) -3.0 V < VEE v -2.375 V (OLS = VEE) 20 5 300 100 5 -100 -600 -400 100 50 900 300 100 -300 -1500 -1000 20 5 300 100 5 -100 -600 -400 100 50 900 300 100 -300 -1500 -1000 20 5 300 100 5 -100 -600 -400 100 50 mA 900 300 100 35 5 100 50 35 5 100 50 35 5 100 50 mA Min Typ Max 0.0 Min 25C Typ Max 0.0 70C(BGA)/85C(QFN)*** Min Typ Max 0.0 Unit V
VEE + 1.2
VEE + 1.2
VEE + 1.2
RTIN IIH
45
50
55
45
50
55
45
50
55
W mA
-300 -1500 -1000
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. Input and output parameters vary 1:1 with VCC. 21. All outputs loaded with 50 W to VCC - 2.0 V. 22. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 23. VIH cannot exceed VCC. |VIH - VTHR| < 2600 mV. 24. VIL always w VEE. |VIL - VTHR| < 2600 mV. 25. VTHR is the voltage applied to one input when running in single-ended mode. *Typicals used for testing purposes. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C.
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NBSG53A
Table 10. AC CHARACTERISTICS for FCBGA-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40C Symbol fmax Characteristic Maximum Frequency (See Figures 4, 6, 8, 10, and 11) (See Figures 5, 7, 9, 10, and 11) (Note 26) DFF DIV/2 Min Typ 8 10 Max Min 25C Typ 8 10 Max Min 70C Typ 8 10 ps 160 150 155 155 165 160 160 160 220 200 215 195 220 200 215 195 210 200 205 205 220 210 215 210 295 270 285 260 290 265 285 260 5 0.5 260 250 255 255 275 260 270 260 370 340 355 325 360 330 355 325 20 1.5 160 155 160 160 170 160 165 160 225 205 220 200 220 200 220 200 215 205 210 210 225 210 220 215 300 275 290 265 295 270 290 265 5 0.5 270 255 260 260 280 260 275 270 375 345 360 330 370 340 360 330 20 1.5 165 160 160 160 170 160 165 165 225 205 220 200 220 200 220 200 220 210 215 215 225 210 220 220 300 275 290 265 295 270 290 265 5 0.5 275 260 270 270 280 260 275 275 375 345 360 330 370 340 360 330 20 1.5 ps ps Max Unit GHz
tPLH, tPHL
Propagation Delay to Output Differential CLKQ, Q (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) **(OLS = VEE) SELQ, Q (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) **(OLS = VEE) RQ, Q (OLS = VCC) DIV/2 (OLS = VCC) DFF (OLS = VCC - 0.4 V) DIV/2 (OLS = VCC - 0.4 V) DFF (OLS = VCC -0.8 V, OLS = FLOAT) DIV/2 (OLS = VCC - 0.8 V, OLS = FLOAT) DFF **(OLS = VEE) DIV/2 **(OLS = VEE) DFF
tSKEW tJITTER
Duty Cycle Skew (Notes 27 and 29) DFF RMS Random Clock Jitter fin v 8 GHz (See Figures 4 and 6) (Note 26) Peak-to-Peak Data Dependent Jitter fin = 8 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 28) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) **(OLS = VEE) 30 20 25 25 30 25 40 75
TBD 2600 75 2600 75 2600 mV ps
VINPP tr tf
50 40 45 45 14 12 9
65 60 65 65
30 20 25 25 30 25 40
50 40 45 45 10 7 12
65 60 65 65
30 20 25 25 30 25 40
50 40 45 45 13 9 10
65 60 65 65 ps ps ps
ts th trr
Setup Time Hold Time Reset Recovery
DCLK DCLK DFF, DIV/2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 26. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to VCC - 2.0 V. Input edge rates is 40 ps (20% - 80%). 27. See Figure 14. tSKEW = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 28. VINPP (MAX) cannot exceed VCC - VEE (Applicable only when VCC - VEE < 2600 mV). 29. See Figure 10. Duty Cycle % vs. Frequency. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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NBSG53A
Table 11. AC CHARACTERISTICS for QFN-16
VCC = 0 V; VEE = -3.465 V to -2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V -40C Symbol fmax Characteristic Maximum Frequency (See Figures 4, 6, 8, 10, and 11) (See Figures 5, 7, 9, 10, and 11) (Note 30) DFF DIV/2 150 160 215 195 Min Typ 8 10 215 190 280 270 5 0.5 285 280 375 345 20 1 150 160 215 195 Max Min 25C Typ 8 10 215 190 280 270 5 0.5 285 280 375 345 20 1 150 160 215 195 Max Min 85C Typ 8 10 ps 215 190 280 270 5 0.5 285 280 375 345 20 1 ps ps Max Unit GHz
tPLH, tPHL
Propagation Delay to Output Differential (Note 34) CLKQ, Q SELQ, Q RQ, Q DIN/2 DFF Duty Cycle Skew (Notes 31 and 33) DFF RMS Random Clock Jitter fin v 8 GHz (See Figures 4 and 6) (Note 30) Peak-to-Peak Data Dependent Jitter fin = 8 Gb/s Input Voltage Swing/Sensitivity (Differential Configuration) (Note 32) Output Rise/Fall Times (20% - 80%) @ 1 GHz Q, Q (OLS = VCC) (OLS = VCC - 0.4 V) (OLS = VCC - 0.8 V, OLS = FLOAT) **(OLS = VEE)
tSKEW tJITTER
TBD 75 2600 75
TBD 2600 75
TBD 2600 mV ps
VINPP tr tf
28 15 25 20 30 25 40
40 40 35 35 14 12 9
65 65 65 65
28 15 25 20 30 25 40
40 40 35 35 10 7 12
65 65 65 65
28 15 25 20 30 25 40
40 40 35 35 13 0 10
65 65 65 65 ps ps ps
ts th trr
Setup Time Hold Time Reset Recovery
DCLK DCLK DFF, DIV/2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 30. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 W to VCC - 2.0 V. Input edge rates is 40 ps (20% - 80%). 31. See Figure 14. tSKEW = |tPLH - tPHL| for a nominal 50% differential clock input waveform. 32. VINPP (MAX) cannot exceed VCC - VEE (Applicable only when VCC - VEE < 2600 mV). 33. See Figure 10. Duty Cycle % vs. Frequency. 34. For all OLS Configuration. **When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE. ***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70C and devices packaged in QFN-16 have maximum ambient temperature specification of 85C.
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NBSG53A
900 OLS = VCC 800 OUTPUT VOLTAGE AMPLITUDE 700 600 500 400 300 200 100 RMS JITTER 0 0 1 2 3 4 5 6 7 8 9 10 11 0 12 OLS = VCC - 0.4 V *OLS = VEE OLS = VCC - 0.8 V, OLS = FLOAT 8 JITTEROUT ps (RMS) 7 6 5 4 3 2 1 9
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) for DFF Mode (VCC - VEE = 3.3 V @ 255C; Repetitive 1010 Input Data Pattern)
900 OLS = VCC OUTPUT VOLTAGE AMPLITUDE 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 OLS = VCC - 0.4 V *OLS = VEE OLS = VCC - 0.8 V, OLS = FLOAT
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) for DIV/2 Mode (VCC - VEE = 3.3 V @ 255C)
*When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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NBSG53A
900 800 OUTPUT VOLTAGE AMPLITUDE 700 600 500 400 300 200 100 RMS JITTER 0 0 1 2 3 4 5 6 7 8 9 10 11 0 12 OLS = VCC - 0.4 V *OLS = VEE OLS = VCC 9 8 JITTEROUT ps (RMS) 7 6 5 4 3 2 1
OLS = VCC - 0.8 V, OLS = FLOAT
INPUT FREQUENCY (GHz)
Figure 6. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) for DFF Mode (VCC - VEE = 2.5 V @ 255C; Repetitive 1010 Input Data Pattern)
900 800 OUTPUT VOLTAGE AMPLITUDE 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 OLS = VCC - 0.4 V OLS = VEE OLS = VCC
*OLS = VCC - 0.8 V, OLS = FLOAT
INPUT FREQUENCY (GHz)
Figure 7. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) for DIV/2 Mode (VCC - VEE = 2.5 V @ 255C)
*When an output level of 400 mV is desired and VCC - VEE > 3.0 V, a 2 kW resistor should be connected from OLS to VEE.
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NBSG53A
1200 1100 1000 900 VOH/VOL (mV) 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 12 VOL (Q) VOL (Q) VOH (Q) VOH (Q)
INPUT FREQUENCY (GHz)
Figure 8. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DFF Mode (VCC - VEE = 3.3 V @ 255C and OLS = VCC - 0.8 V, OLS = FLOAT)
1200 1100 1000 900 VOH/VOL (mV) 800 700 600 500 400 300 200 100 0 0 1 2 3 4
VOH (Q)
VOH (Q)
VOL (Q)
VOL (Q)
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 9. VOH/VOL (Q/Q) vs. Input Frequency (fin) for DIV/2 Mode (VCC - VEE = 3.3 V @ 255C and OLS = VCC - 0.8 V, OLS = FLOAT)
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NBSG53A
100 90 80 DUTY CYCLE (%) 70 DIV/2 Mode 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 11 12 DFF Mode
INPUT FREQUENCY (GHz)
Figure 10. Duty Cycle % vs. Input Frequency (fin) (VCC - VEE = 3.3 V @ 255C)
100 90 80 DUTY CYCLE (%) 70 DIV/2 Mode 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 11 12 DFF Mode
INPUT FREQUENCY (GHz)
Figure 11. Duty Cycle % vs. Input Frequency (fin) (VCC - VEE = 2.5 V @ 705C)
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NBSG53A
300 200 100 0 IOLS (mA) -100 -200 -300 -400 -500 -600 -700 VCC VCC - 400 VCC - 800 VOLS (mV) VCC - 1200 VEE
Figure 12. Typical OLS Input Current vs. OLS Input Voltage (VCC - VEE = 3.3 V @ 255C)
1000 VCC - 75 800 VCC - 700 600 VEE + 100 400 VCC - 250 200 VCC - 1125 0 VCC VCC - 400 VCC - 800 OLS (mV) VCC - 1200 VEE VCC - 1275 VCC - 550 VCC - 900
Voutpp (mV)
Figure 13. OLS Operating Area
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NBSG53A
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 14. AC Reference Measurement
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 15. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020/D - Termination of ECL Logic Devices)
ORDERING INFORMATION
Device NBSG53ABA NBSG53ABAR2 NBSG53AMN NBSG53AMNR2 Package Type 4x4 mm FCBGA-16 4x4 mm FCBGA-16 3x3 mm QFN-16 3x3 mm QFN-16 Shipping 100 Units / Tray 500 / Tape & Reel 123 Units / Rail 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NBSG53A
PACKAGE DIMENSIONS
FCBGA-16 BA SUFFIX PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE CASE 489-01 ISSUE O
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
-X- D M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC
-Y- K E
M 0.20
3X FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D
e
4
3
2
1
3
16 X
b 0.15 0.08
M M
S VIEW M-M
ZXY Z
5 0.15 Z A A2 -Z-
A1
16 X
4 DETAIL K
0.10 Z
ROTATED 90 _ CLOCKWISE
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NBSG53A
PACKAGE DIMENSIONS
QFN-16 MN SUFFIX CASE 485G-01 ISSUE O
-X- A M -Y-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A B C D E F G H J K L M N P R SEATING PLANE MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
C K -T-
L
4
9
F
1 12
16
13
P
D
NOTE 3 M
0.10 (0.004)
TXY
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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18
NBSG53A/D

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